1. Technical Field
The present invention relates in general to electronic circuitry and, in particular, to dynamic logic digital circuitry. Still more particularly, the present invention relates to reduced power dynamic logic circuitry that inhibits the reevaluation of logic inputs during clock cycles in which the logic inputs remain unchanged.
2.Description of the Related Art
As integrated circuits have achieved higher clock speeds and are fabricated with ever increasing densities, power dissipation has become a primary consideration in integrated circuit design. While the need for reduced power integrated circuits is of particular concern in the design of battery-powered devices such as portable computers, applications for reduced-power integrated circuits extend to desktop computer systems and other electronic devices due to power supply and heat dissipation considerations.
As is well-known to those skilled in the art, a conventional dynamic logic integrated circuit divides a clock cycle into precharge and evaluate phases. During the precharge phase, the dynamic logic circuit is preset to a known logic state, and during the evaluate phase, the logic inputs of the dynamic logic circuit are evaluated by circuitry that implements a logic function to determine a logic output. Importantly, a conventional dynamic logic circuit evaluates its logic inputs during the evaluate phase of each cycle, and accordingly consumes switching power during each cycle.
Therefore, a need arises for a reduced-power dynamic logic circuit.